Phase Locked Loop (PLL) Expert to Review Clock Generators

Case Description:

A phase locked loop circuit expert was needed to review both analog and digital phase lock loop (PLL) circuit technology in microprocessor clock generators for a patent infringement case. The patent related to a clock generator employing a circuit known as a phase locked loop. Phase locked loop systems, or PLL's, are widely used in radio, telecommunications, computers and other microelectronics. Clock generators employing a PLL have a wide range of application within the microelectronics industry.

For this patent infringement case, IMS ExpertServices was asked to locate a mixed signal integrated circuit design expert who design experience in both analog and digital PLL circuits. Expertise in the technical problems and conventional solutions associated with PLL clock generators was preferred.

Experts Presented:

  • Integrated Circuit Design

    This mixed signal integrated circuit design expert has over 30 years of industry experience as an electrical engineer. He specializes in analog and mixed signal integrated circuit design and testing. He earned his B.S., M.S, and Ph.D. in electrical engineering and is a member of the IEEE and NSPE. He established an engineering company which has provided custom integrated analog and mixed signal circuit design to the microelectronics industry for over a decade. Many of this phase locked loop expert’s design projects over the years have employed PLLs across a wide range of speeds. IMS Reference #5010421

  • Integrated Circuit Design

    This integrated circuit design expert has nearly fifteen years of experience in the microelectronics industry and academia. He specializes in phase lock loop (PLL) and integrated circuit (IC) design. His research interests include self-calibrating analog-to-digital converter design, low jitter and phase noise oscillator design, and mixed signal integrated circuit characterization. He obtained his Ph.D. in electrical engineering and is both a member of ASEE and a senior member of IEEE. Considered a PLL expert within the IC industry, his expertise in PLL and mixed signal integrated circuit design is widely recognized and respected. His research has generated wide-spread acclaim among his peers in the field, which has led to a string of consulting assignments and subsequent research in mixed signal integrated circuit design. IMS Reference #5010435

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